The present invention is directed to formation of multilayer printed circuit boards and articles formed thereby.
Multilayer PCB's are typically constructed by interleafing imaged conductive layers such as one containing copper with dielectric layers such as a partially cured B-stage resin, i.e., a prepreg, into a multilayer sandwich which is then bonded together by applying heat and pressure. Since a conductive layer with a smooth copper surface does not bond well to the prepreg, rough copper surfaces have been employed to obtain a better bond to a dielectric. Therefore, a portion of the multilayer PCB industry applies a mechanical roughening process step to assure better bonding. However, as circuit patterns get finer, there is an increasing risk of physically damaging the conductor traces during this surface preparation.
Another process employed by the industry to improve bonding between the conductive layer and the dielectric are various copper surface oxidation procedures widely practiced in the plating industry to assure good interphasial adhesion.
A common drawback for all processes relying mainly on the mechanical interlocking of a rough copper surface with the dielectric is the marginal bond strength with polyimide prepreg and the fact that there is no flexible bonding interphase to absorb the stresses originating from the different thermal expansion coefficients of copper and dielectric which can cause thermal shock failures.
Other technologies to improve bonding of conductive layers to dielectric layers in multilayer boards are described in U.S. Pat. No. 3,536,546, as well as European Patent Application 216,531 and also to U.S. Pat. No. 4,657,632, and involve the deposition of tin on the conductive layer prior to bonding. Whereas these techniques give improved bond strength compared to a copper surface, yield a surface less susceptible to mechanical damage than copper oxide, and require only ambient temperature processing in a less corrosive environment than copper oxide treatments, the resulting bond strengths are considered to be comparable to copper oxide on epoxy prepreg, and inferior to brown oxide on polyimide prepreg. Also the bond strength can deteriorate with time at elevated temperatures, as does the oxide bond. In addition, delamination after solder shock is occasionally observed.
An example of disclosure of a black oxide layer on a copper clad laminate as a step in the process of preparing multilayer circuit boards is disclosed in U.S. Pat. No. 4,512,818. The major drawbacks of these procedures are considered to be marginal bond strength on polyimide prepregs, corrosivity and high temperature processing, a surface coating prone to mechanical damage, partial delamination around through-holes called "pink ring" due to the removal of the bonding oxide layer by aggressive (acidic, reductive) hole cleaning chemicals, and a decay of the bond strength with time at elevated temperatures.
The formation of conductive layer topographies particularly suitable to improved bonding with prepreg without the drawbacks of the oxide treatments have been recently described at the Printed Circuit World Conference IV, Tokyo, Japan, June 2-5, 1987. H. Akahoshi et al. (WCIV-9) describe the formation of a surface oxide which gets removed prior to bonding, leaving a copper surface with roughness and bonding characteristics comparable to the oxide surface. Nakaso et al. (WCIV-10) describe the formation of a rough conductive layer surface by forming an electroless copper deposit on the conductive layer for better bonding. Silanes, deposited on this clean metallic copper surface are reported to yield a marginal increase in bond strength.
Likewise, U.S. Pat. No. 3,508,983 discloses the use of gamma-amino propyl triethoxysilane to bond copper to a polyester base adhesive in the manufacture of a printed circuit board. This reference emphasizes the point that copper oxide should be removed prior to the silane treatment to affect good bonding.
U.S. Pat. No. 4,499,152 discloses formation of a metal laminate with utility of high resolution printed circuit patterns. The laminate preferably contains a resin-bonded, glass reinforced substrate, a layer of coupling agent covering and bonded to a major surface of the substrate and a layer of ultra-thin copper adjacent the layer of coupling agent, and a composite bonding layer dispersed between the copper layer and the layer of coupling agent. A disclosure class of coupling agents includes organosilanes.
European Patent Application 88115951.1, published as 0310010 on Apr. 5, 1989, discloses a process for forming multilayer printed circuit boards wherein a ureido silane is used to improve adhesion between tin-plated copper circuitry and the cured insulating layer during subsequent soldering operations. While this process is generally effective when the resulting laminates are prebaked before soldering, in some instances when prebaking is not employed delamination can occur during soldering.